A2O, Microwatt, and open-source IBM POWER10 design — datacenter-proven POWER ISA cores with decades of HPC and enterprise pedigree. The OPF E1 Working Group consolidates these into a unified enterprise-grade silicon core for HPC, AI inference, and sovereign computing.
Decades of IBM datacenter processor engineering, now open-source. The OPF E1 working group builds on a lineage stretching from POWER8's OpenPOWER launch to today's freely available RTL.
IBM's 2-thread out-of-order POWER ISA core, fully open-sourced on GitHub. Originally designed for embedded and communications applications, A2O features a full RTL implementation suitable for FPGA prototyping and ASIC tape-out. It served as the network-on-chip compute tile in IBM's BlueGene/Q supercomputer.
Microwatt is IBM's open-source POWER ISA 3.0 soft processor implemented in VHDL. It runs Linux, boots to a shell, and has been extensively validated on multiple FPGA platforms. The OPF Microwatt CPU Hackathon (2025) demonstrated its viability as a foundation for open silicon development and community collaboration.
IBM POWER10 introduced POWER ISA 3.1 with Matrix Math Assist (MMA) extensions — delivering 4× the AI inference throughput per core versus POWER9. The OPF E1 working group is engaged with IBM to incorporate open-source POWER10 design elements, bringing this proven 7nm datacenter architecture into the open silicon ecosystem.
The OPF E1 working group targets the full datacenter feature set: hardware virtualization, ECC memory, high-bandwidth interconnects, and the Matrix Math Assist (MMA) extensions for AI/ML workloads — all based on open RTL that any member can inspect, modify, and contribute to.
A2O and Microwatt are already open on GitHub under Apache 2.0. The OPF E1 working group is forming to review, consolidate, and extend these cores toward a unified ISA 3.1 enterprise target.
Enterprise and hyperscale computing demands a fully open processor — one where every register, pipeline stage, and cache hierarchy can be audited. OPF E1 is built for that world.
Following in BlueGene/Q's footsteps, OPF E1 targets national labs, research institutions, and scientific workloads requiring verified, open-source compute fabric with strong floating-point performance.
POWER ISA 3.1's Matrix Math Assist (MMA) extensions deliver dense matrix operations for transformer inference and training. OPF E1 brings open silicon to the AI accelerator market.
OpenPOWER servers already run in hyperscale environments. An open-RTL E1 core enables cloud operators to fully customize, audit, and optimize their compute silicon stack.
Governments requiring fully auditable, domestically manufactured processors will benefit from OPF E1's open RTL and fab-at-Intel-or-TSMC strategy, eliminating supply chain blind spots.
POWER architecture has long dominated mission-critical database workloads with IBM i and AIX. OPF E1 extends this legacy to open silicon deployable by any organization.
DoD and intelligence community requirements for Trusted Foundry silicon align with OPF E1's Intel 18A fab target — a DMEA-certified US domestic process at 1.8nm-class geometry.
The OPF E1 Working Group takes the best of A2O, Microwatt, and open-source IBM POWER10 design and produces a single, unified open-source enterprise processor core targeting modern foundry processes.
Deep review of A2O pipeline, Microwatt VHDL, and IBM POWER10 open-source design to identify the strongest elements from each for consolidation into the OPF E1 baseline.
Extend the consolidated baseline to full POWER ISA 3.1 compliance including Matrix Math Assist extensions for AI/ML, prefix instructions, and vector enhancements.
AI-assisted EDA flows via the Silicon Factory, targeting 7/5nm processes at Intel Foundry, Samsung, and TSMC for verified silicon availability.
Help define the architecture of the world's first fully open-source, enterprise-grade POWER ISA processor. Members from IBM, academia, national labs, and industry are welcome.
