OpenCAPI delivered direct, cache-coherent, high-bandwidth connectivity between POWER processors and accelerators — specified publicly, proven in production, and still fully documented. Osmosis is the OpenPOWER Foundation initiative to bring this technology forward as the open coherent interconnect for sovereign AI compute. The specs are archived. The reference designs are on GitHub. The opportunity is now.
Osmosis is built on the OpenCAPI specification — a direct, cache-coherent, high-bandwidth interface between POWER processors and accelerators. Open, auditable, and implementable by anyone.
The open interconnect opportunity: Coherent accelerator fabric — the technology that enables direct, low-latency connectivity between processors and AI accelerators at memory speeds — has historically required fully auditable, open specifications. OpenCAPI provided exactly that: a fully documented, publicly specified standard proven in production across OpenPOWER systems at banks, national labs, and hyperscalers. Osmosis brings this forward.
In August 2022, the OpenCAPI Consortium transferred its trademarks and specifications to the CXL Consortium. The specifications remain fully public, the reference designs are on GitHub, and the technology is proven. Osmosis is the path forward — bringing these assets under active OPF stewardship.
IBM, Xilinx, Mellanox, Micron, Google, Toshiba Memory, and HPE form the OpenCAPI Consortium. Specification released publicly. First silicon ships on an OpenPOWER processor.
CompleteOpenPOWER systems ship with OpenCAPI / OMI controllers per socket, delivering 410 GB/s memory bandwidth — validating the technology across production deployments at banks, national labs, and hyperscalers.
CompleteOpenCAPI Consortium signs letter of intent to transfer all assets — trademarks, specifications, OMI spec — to the CXL Consortium. Open-source GitHub IP remains available.
IP transferredSpecs are archived and downloadable. FPGA reference designs are on GitHub. OPF is working with the original consortium founders to secure a formal patent license that enables the community to build confidently.
Action neededPatent license secured → FPGA reference implementation officially sanctioned → third-party POWER licensees add OpenCAPI ports to ASIC designs → complete open coherent accelerator fabric for sovereign AI compute.
Unlocked by this initiativeOsmosis and CXL are complementary, not competing: CXL is a PCIe protocol — it runs on the PCIe physical layer and excels at memory pooling and disaggregation. OpenCAPI used dedicated high-speed SerDes wired directly to the POWER memory fabric, designed for tight-coupled, cache-coherent, accelerator-attached-at-processor-speed workloads. They solve different problems. Osmosis fills the gap for the coherent, low-latency, high-bandwidth use case that no open standard currently addresses.
Sovereign AI programs require every layer of compute infrastructure to be auditable and open — including the interconnect between processor and accelerator. Osmosis is the only initiative building that open coherent fabric.
Governments and regulated enterprises building sovereign AI compute need every layer of the stack — including the accelerator interconnect — to be fully auditable. Osmosis is the only initiative building an open, documented, coherent accelerator fabric for this market.
For financial regulators, intelligence agencies, and healthcare systems, the interconnect between processor and accelerator sits inside the trust boundary. OpenCAPI's specification was fully public — every layer inspectable — and Osmosis preserves and extends that openness.
The specifications are archived and downloadable. The FPGA reference designs are live on GitHub. Microwatt (OPF's open POWER soft core) runs on commodity FPGAs. The only missing piece is a clear IP license that allows the community to build without legal uncertainty.
The original OpenCAPI Consortium founding members built the technology that Osmosis is building on. We are inviting each of them to formally grant royalty-free (or FRAND) patent coverage to OpenPOWER Foundation members — the same model that made the POWER ISA an open ecosystem.
Built on precedent: In 2019, IBM transferred the POWER ISA to the OpenPOWER Foundation under an open licence. That single act unlocked an entire ecosystem of open processors, compilers, and firmware. An OpenCAPI patent license grant completes the open hardware stack from ISA to interconnect — the same proven model applied to a new layer.
With the patent license in place, a community that already has the specs, the reference designs, and the processor ISA can move forward with confidence — from FPGA prototypes to ASIC integration to a complete open sovereign stack.
Wire the existing OC-Accel FPGA framework into Microwatt (OPF's open POWER soft core). Running today on commodity FPGAs. An IP grant makes this a formally sanctioned OPF reference implementation — opening the path for every OPF member to build on a legally clear foundation.
POWER ISA licensees building their own chips — including emerging fabs in India, Africa, and Southeast Asia — can add OpenCAPI ports to their designs. The foundry SerDes IP is available from TSMC and Samsung on standard process nodes.
Vendors building inference accelerators, HSMs, and SmartNICs for the POWER ecosystem can implement OpenCAPI endpoints — enabling direct memory-coherent AI inference offload with lower latency and higher bandwidth than PCIe.
Open ISA (POWER) + open coherent fabric (OpenCAPI) + open accelerator designs + open firmware (OpenBMC/OpenFSP) = a fully auditable, sovereign AI compute stack with no closed components in the critical path.
While the IP grant process is underway, the existing open-source implementations are available for development and evaluation.
If your organisation depends on open, auditable compute infrastructure — or if you represent one of the founding consortium members — we want to hear from you. The path from archived spec to working open ecosystem starts with this conversation.
