GameCube, Wii, Wii U, Xbox 360, PlayStation 3 — all ran on IBM POWER-based silicon. We're bringing these legendary cores into the open: open-sourced, updated to current POWER ISA, and verified through modern EDA flows.
Every one of these CPUs shipped in hundreds of millions of units. They were designed by IBM, built on cutting-edge process nodes of their era, and optimised for real-time graphics workloads. That design heritage is what we're bringing back into the open.
The Gekko introduced paired-single floating-point SIMD — essentially a gaming-specific vector unit baked into PowerPC. Running 485 million instructions per second on 0.18 µm copper interconnect, it was IBM's most advanced consumer chip of its era. The architectural insight — tight SIMD integration with scalar POWER — remains relevant for today's embedded AI workloads.
Open-source initiative — in planningBroadway was a 729 MHz refinement of Gekko shrunk to 90 nm (later 65 nm). The architectural additions focused on motion-processing integration for the Wii Remote and improved memory subsystem timing. As a die-shrink of the Gekko architecture, Broadway demonstrates the power scaling properties of this core family — key data for modern process retargeting.
Open-source initiative — in planningEspresso evolved the Broadway family into a tri-core design at 1.243 GHz on 45 nm — a significant multi-core step for the Power Architecture gaming lineage. The 3-core topology with 2 threads each (6 total hardware threads) and 3 MB shared L2 established patterns that directly inform modern chiplet interconnect designs. The most architecturally sophisticated of the Nintendo gaming cores.
Open-source initiative — in planningXenon was the most ambitious of the 7th-gen gaming CPUs: three in-order PowerPC cores at 3.2 GHz, each with two VMX (AltiVec) SIMD units — a total of 6 SIMD engines on one die. Microsoft's software team wrote hand-tuned VMX code for every major game. The dual-VMX-per-core topology is a compelling starting point for a modern POWER-based DSP or media processing core.
Open-source initiative — in planningThe Cell's PPE is an in-order dual-threaded PowerPC core acting as the control processor for 8 Synergistic Processing Elements (SPEs) — 128-bit SIMD vector processors with their own local store memory. This heterogeneous POWER + vector architecture prefigured modern CPU+AI accelerator chiplet designs by nearly 20 years.
The Cell Broadband Engine's heterogeneous design — a POWER core orchestrating eight independent SIMD vector processors via a high-speed ring bus — is architecturally ahead of its time. Each SPE has 256 KB of local store, its own DMA engine, and runs independently of the PPE. The entire topology maps directly onto modern disaggregated chiplet architectures with a CPU control die and vector/AI compute tiles.
We're evaluating the Cell PPE as a foundation for a modern heterogeneous POWER core with pluggable accelerator tiles — directly applicable to AI inference, media processing, and real-time control systems.
The gaming cores weren't toys. They were IBM's most advanced commercial silicon of their era — hand-optimised for real-time, power-constrained, high-throughput workloads. That's exactly what today's edge AI and embedded systems market demands.
Gaming CPUs are built for deterministic latency — no GC pauses, no unpredictable page faults, strict real-time guarantees. The same properties make them ideal for embedded control, automotive compute, and edge inference where latency variance is failure.
Console TDP budgets were tight — 10–50W total system. The gaming cores squeezed maximum throughput from minimal watts. Open-sourcing them gives embedded designers a starting point already optimised for the power envelope that matters in battery-powered and fanless devices.
Gekko's paired-single SIMD, Xenon's dual-VMX per core, Cell's SPE vector units — all represent sophisticated vector compute approaches that predate modern AI accelerator design by a decade. The architectural patterns are directly relevant to new ML inference and DSP workloads.
Updated to modern POWER ISA, these cores gain 30+ years of software compatibility — Linux, GCC, LLVM, and the full open-source toolchain. Designs built on gaming heritage cores get a full software stack on day one, not a porting project.
These chips shipped in hundreds of millions of units. The architectural decisions survived contact with real software, real games, real workloads. Open-source cores starting from that baseline are fundamentally different from academic designs — they carry production validation.
Updated RTL through IBM EDA Suite flows via the Silicon Factory targeting advanced process nodes gives orders-of-magnitude improvements in power, area, and frequency over the original process nodes. A Gekko at 7 nm would run at several GHz with a fraction of the original power budget.
These gaming cores are the reference material — not the final product. The OPF G1 Working Group synthesises the best architectural ideas from all five platforms into a single unified OPF G1 core, then takes it through ISA 3.1 update, AI-assisted EDA flows via the IBM EDA Suite and Silicon Factory, and tape-out at Intel Foundry, Samsung, or TSMC targeting 7/5nm.
Work with IP holders and the broader POWER community to release Verilog/VHDL RTL for the gaming heritage cores under an open licence (Apache 2.0 target).
Bring the gaming cores from PowerPC 2.02 / Book E / BookS legacy ISA up to OpenPOWER ISA 3.1 — gaining 30+ years of software compatibility and open ISA governance.
Run the updated cores through IBM EDA Suite flows via the Silicon Factory — synthesis, P&R, timing sign-off — targeting FPGA bring-up first, then ASIC on modern process nodes.
Whether you're a hardware engineer, a chip historian, a gaming community member, or someone who reverse-engineered these consoles as a hobby — there is a role for you in this initiative. We need RTL contributors, ISA experts, EDA flow engineers, and people who simply care about preserving and advancing POWER's gaming legacy.
Also see: N1 · Networking Core · Silicon Factory
