Freescale PowerQUICC and QorIQ processors powered Cisco routers, Juniper switches, and industrial networking equipment for two decades. We're open-sourcing this proven networking silicon, updating it to POWER ISA 3.1, and running it through modern EDA flows.
Freescale (formerly Motorola, acquired by NXP) built three successive generations of POWER-based networking processors. Each generation ran in real production networks at scale — not lab silicon, not reference designs. Production iron that carried internet traffic for two decades.
The MPC85xx was the mid-range router CPU for a decade. Book E PowerPC with hardware network acceleration, integrated Ethernet MACs, PCI Express, and dedicated crypto engines. The e500 core's split integer/FP pipeline and deterministic memory latency made it the default choice for control-plane packet processing across the industry.
The P4080 — 8 e500mc cores at 1.5 GHz on 45 nm — was the carrier-grade networking CPU of its era. The QorIQ line introduced DPAA (Data Path Acceleration Architecture), a hardware packet classification and scheduling engine integrated directly with the CPU complex. DPAA prefigured modern SmartNIC architectures by a decade. The P5040 pushed to 2.2 GHz with e5500 64-bit cores and hardware virtualisation.
AppliedMicro (APM) built access-layer switch SoCs around PowerPC 465/476 cores integrated with a network processing unit and switch fabric on a single die. The APM86392 shipped in Cisco Catalyst 2960X and 3650/3850 series — the most widely deployed access switches in enterprise networking. Tight CPU-NPU integration on a single die at 40 nm represented the state of the art for cost-optimised access networking.
The QorIQ P4080's Data Path Acceleration Architecture integrated hardware packet classification, policing, scheduling, and queue management directly adjacent to the CPU complex — connected via a coherent fabric. This is identical to what NVIDIA Bluefield, Marvell Octeon, and Broadcom Stingray SmartNICs do today. Open-sourcing DPAA gives designers a 45 nm reference for a hardware-accelerated networking data path that can be updated to modern nodes.
These weren't reference platforms. They were production CPUs in equipment that carried enterprise and carrier internet traffic for 10–20 years. That deployment history is the validation data that academic designs never have.
RISC-V has open CPU cores. POWER has open CPU cores. But network processing — the packet classification, scheduling, and forwarding silicon that sits between the CPU and the wire — remains almost entirely proprietary. The QorIQ DPAA changes that.
QorIQ DPAA is the original SmartNIC architecture — POWER CPU plus hardware packet processing, coherently connected. Open-sourcing it gives SmartNIC designers a 45 nm reference with proven silicon validation to port to modern nodes.
Nations building sovereign networking equipment need open-source control-plane silicon they can audit, modify, and build themselves. PowerQUICC and QorIQ — updated to POWER ISA 3.1 and EDA-verified — provide the foundation for fully auditable national networking infrastructure.
Network protocols are big-endian. The POWER ISA is big-endian. Software written for PowerQUICC and QorIQ handles Ethernet frames, IP headers, and MPLS labels without byte-swapping overhead — a performance advantage that disappears when porting to x86 or ARM little-endian platforms.
The e500/e500mc pipeline was designed for deterministic execution timing — critical for line-rate packet forwarding. General-purpose OoO processors optimise for average throughput; networking CPUs optimise for worst-case latency. That design philosophy is preserved in the heritage cores.
A QorIQ P4080 at 7 nm with updated ISA would deliver tens of Gbps of deterministic packet processing with POWER's software ecosystem. The architecture is proven; the opportunity is in process shrink and ISA modernisation through the IBM EDA Suite via the Silicon Factory.
The QorIQ P-series fabric-connected multi-core design maps naturally onto modern disaggregated chiplet architectures — a CPU tile plus network acceleration tiles, connected via UCIe or proprietary interconnect. The architectural insight has aged well.
These networking cores are the reference material — not the final product. The OPF N1 Working Group takes the best from PowerQUICC, QorIQ DPAA, and APM86xxx — especially the DPAA packet acceleration model — and consolidates them into a single unified OPF N1 networking core. That core then goes through ISA 3.1 update, AI-assisted EDA verification, and tape-out at Intel Foundry, Samsung, or TSMC at 7/5nm.
Engage NXP (Freescale successor), APM (acquired by Macom/Inphi), and the broader networking hardware community to release RTL for key networking cores under open licences.
Migrate the e500 Book E / e500mc cores from their legacy ISA variant to OpenPOWER ISA 3.1, enabling the full modern POWER software toolchain and 30 years of binary compatibility.
Run the updated networking cores through IBM EDA Suite flows via the Silicon Factory — synthesis, timing sign-off, and physical verification — targeting FPGA bring-up and ASIC on advanced process nodes.
Network engineers, chip designers, embedded Linux developers, open networking advocates, and hardware reverse engineers all have a role to play. If you worked on PowerQUICC or QorIQ-based systems, or if you want to build the next generation of open networking silicon on POWER, this is where to start.
Also see: G1 · Gaming Core · Silicon Factory
